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HB288256C5/HB288192C5 HB288160C5/HB288128C5 HB288096C5/HB288064C5 HB288032C5
CompactFlashTM 256 MByte/192 MByte/160 MByte/128 MByte 96 MByte/64 MByte/32 MByte
ADE-203-951D (Z) Rev. 3.0 Oct. 23 2000 Description
HB288256C5, HB288192C5, HB288160C5, HB288128C5, HB288096C5, HB288064C5, HB288032C5 are CompactFlashTM. This card complies with CompactFlashTM specification, and is suitable for the usage of data storage memory medium for PC or any other electric equipment and digital still camera. This card is equipped with Hitachi 256 Mega bit Flash memory. This card is suitable for ISA (Industry Standard Architecture) bus interface standard, and read/write unit is 1 sector (512 bytes) sequential access. By using this card it is possible to operate good performance for the system which have CompactFlashTM slots. Note: CompactFlashTM is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA which in turn will license it royalty-free to CFA members. *CFA: CompactFlashTM Association.
Features
* CompactFlashTM specification standard 50 pin two pieces connector and Type I (3.3 mm) * 3.3V / 5V single power supply operation * Card density is 256 Mega bytes maximum This card is equipped with Hitachi 256 Mega bit Flash memory
HB288256/192/160/128/096/064/032C5
* 3 variations of mode access Memory card mode I/O card mode True IDE mode * Internal self-diagnostic program operates at VCC power on * High reliability based on internal ECC (Error Correcting Code) function * Data write is 300,000 cycles * Data reliability is 1 error in 10 14 bits read * Auto sleep mode
Card Line Up*1
Type No. HB288256C5 HB288192C5 HB288160C5 HB288128C5 HB288096C5 HB288064C5 HB288032C5 Notes: 1. 2. 3. 4. Card density Capacity* 4 256 MB 192 MB 160 MB 128 MB 96 MB 64 MB 32 MB Total sectors/ Sectors/ card* 3 track* 2 48 32 32 32 32 32 32 Number of head 15 15 10 8 8 4 4 Number of cylinder 695 782 978 978 732 978 489
256,204,800 byte 500,400 192,184,320 byte 375,360 160,235,520 byte 312,960 128,188,416 byte 250,368 95,944,704 byte 64,094,208 byte 32,047,104 byte 187,392 125,184 62,592
These data are written in ID. Total tracks = number of head x number of cylinder. Total sectors/card = sectors/track x number of head x number of cylinder. It is the logical address capacity including the area which is used for file system.
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Card Pin Assignment
Memory card mode Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Signal name GND D3 D4 D5 D6 D7 -CE1 A10 -OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP -CD2 -CD1 D11 D12 D13 D14 I/O -- I/O I/O I/O I/O I/O I I I I I I -- I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O card mode Signal name GND D3 D4 D5 D6 D7 -CE1 A10 -OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 -IOIS16 -CD2 -CD1 D11 D12 D13 D14 I/O -- I/O I/O I/O I/O I/O I I I I I I -- I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O True IDE mode Signal name GND D3 D4 D5 D6 D7 -CE1 A10 -ATASEL A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 -IOIS16 -CD2 -CD1 D11 D12 D13 D14 I/O -- I/O I/O I/O I/O I/O I I I I I I -- I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O
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Memory card mode Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal name D15 -CE2 -VS1 -IORD -IOWR -WE RDY/-BSY VCC -CSEL -VS2 RESET -WAIT -INPACK -REG BVD2 BVD1 D8 D9 D10 GND I/O I/O I O I I I O -- I O I O O I I/O I/O I/O I/O I/O -- I/O card mode Signal name D15 -CE2 -VS1 -IORD -IOWR -WE -IREQ VCC -CSEL -VS2 RESET -WAIT -INPACK -REG -SPKR -STSCHG D8 D9 D10 GND I/O I/O I O I I I O -- I O I O O I I/O I/O I/O I/O I/O -- True IDE mode Signal name D15 -CE2 -VS1 -IORD -IOWR -WE INTRQ VCC -CSEL -VS2 -RESET IORDY -INPACK -REG -DASP -PDIAG D8 D9 D10 GND I/O I/O I O I I I O -- I O I O O I I/O I/O I/O I/O I/O --
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Card Pin Explanation
Signal name Direction Pin No. Description A10 to A0 I (PC Card Memory mode) A10 to A0 (PC Card I/O mode) A2 to A0 (True IDE mode) BVD1 I/O (PC Card Memory mode) -STSCHG (PC Card I/O mode) -PDIAG (True IDE mode) BVD2 I/O (PC Card Memory mode) -SPKR (PC Card I/O mode) -DASP (True IDE mode) -CD1, -CD2 O (PC Card Memory mode) -CD1, -CD2 (PC Card I/O mode) -CD1, -CD2 (True IDE mode) -CE1, -CE2 I (PC Card Memory mode) Card Enable -CE1, -CE2 (PC Card I/O mode) Card Enable -CE1, -CE2 (True IDE mode) -CE2 is used for select the Alternate Status Register and the Device Control Register while -CE1 is the chip select for the other task file registers. 7, 32 -CE1 and -CE2 are low active card select signals. Byte/Word/Odd byte mode are defined by combination of -CE1, -CE2 and A0. 26, 25 45 18, 19, 20 46 Address bus is A10 to A0. Only A2 to A0 are used, A10 to A3 should be grounded by the host. BVD1 outputs the battery voltage status in the card. This output line is constantly driven to a high state since a battery is not required for this product. -STSCHG is used for changing the status of Configuration and status register in attribute area. -PDIAG is the Pass Diagnostic signal in Master/Slave handshake protocol. BVD2 outputs the battery voltage status in the card. This output line is constantly driven to a high state since a battery is not required for this product. -SPKR outputs speaker signals. This output line is constantly driven to a high state since this product does not support the audio function. -DASP is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. -CD1 and -CD2 are the card detection signals. -CD1 and -CD2 are connected to ground in this card, so host can detect that the card is inserted or not. 8, 10, 11, 12, 14, Address bus is A10 to A0. A10 is MSB and A0 is 15, 16, 17, 18, LSB. 19, 20
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Signal name Direction Pin No. 39 Description This signal is not used. -CSEL I (PC Card Memory mode) -CSEL (PC Card I/O mode) -CSEL (True IDE mode) This signal is used to configure this device as a Master or a Slave when configured in the True IDE mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. Data bus is D15 to D0. D0 is the LSB of the even byte 31, 30, 29, 28, 27, 49, 48, 47, 6, of the word. D8 is the LSB of the odd byte of the 5, 4, 3, 2, 23, 22, word. 21
D15 to D0 I/O (PC Card Memory mode)
D15 to D0 (PC Card I/O mode) D15 to D0 (True IDE mode) GND -- (PC Card Memory mode) GND (PC Card I/O mode) GND (True IDE mode) -INPACK O (PC Card Memory mode) -INPACK (PC Card I/O mode) Input Acknowledge 43 This signal is not used and should not be connected at the host. This signal is asserted low by this card when the card is selected and responding to an I/O read cycle at the address that is on the address bus during -CE and -IORD are low. This signal is used for the input data buffer control. This signal is not used and should not be connected at the host. 34 This signal is not used. -IORD is used for control of read data in I/O task file area. This card does not respond to -IORD until I/O card interface setting up. -IORD is used for control of read data in I/O task file area. This card does not respond to -IORD until True IDE interface setting up. 1, 50 Ground
-INPACK (True IDE mode) -IORD I (PC Card Memory mode) -IORD (PC Card I/O mode) -IORD (True IDE mode)
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Signal name Direction Pin No. 35 Description This signal is not used. -IOWR is used for control of data write in I/O task file area. This card does not respond to -IOWR until I/O card interface setting up. -IOWR is used for control of data write in I/O task file area. This card does not respond to -IOWR until True IDE interface setting up. 9 -OE is used for the control of reading register's data in attribute area or task file area. -OE is used for the control of reading register's data in attribute area. To enable True IDE mode this input should be grounded by the host. 37 The signal is RDY/-BSY pin. RDY/-BSY pin turns low level during the card internal initialization operation at VCC applied or reset applied, so next access to the card should be after the signal turned high level. This signal is active low -IREQ pin. The signal of low level indicates that the card is requesting software service to host, and high level indicates that the card is not requesting. This signal is the active high Interrupt Request to the host. 44 -REG is used during memory cycles to distinguish between task file and attribute memory accesses. High for task file, Low for attribute memory is accessed. -REG is constantly low when task file or attribute memory is accessed. This input signal is not used and should be connected to VCC. -IOWR I (PC Card Memory mode) -IOWR (PC Card I/O mode) -IOWR (True IDE mode) -OE I (PC Card Memory mode) -OE (PC Card I/O mode) -ATASEL (True IDE mode) RDY/-BSY O (PC Card Memory mode)
-IREQ (PC Card I/O mode)
INTRQ (True IDE mode) -REG I (PC Card Memory mode) Attribute memory select -REG (PC Card I/O mode) -REG (True IDE mode)
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Signal name Direction Pin No. 41 Description This signal is active high RESET pin. If this signal is asserted high, the card internal initialization begins to operate. During the card internal initialization RDY/-BSY is low. After the card internal initialization RDY/-BSY is high. This signal is active high RESET pin. If this signal is asserted high, the card internal initialization begins to operate. In this mode, RDY/-BSY signal can not be used, so using Status Register the Ready/Busy status can be confirmed. This signal is active low -RESET pin. If this signal is asserted low, all the register's in this card are reset. In this mode, RDY/-BSY signal can not be used, so using status register the Ready/Busy status can be confirmed. 13, 38 +5 V, +3.3 V power. RESET I (PC Card Memory mode)
RESET (PC Card I/O mode)
-RESET (True IDE mode)
VCC -- (PC Card Memory mode) VCC (PC Card I/O mode) VCC (True IDE mode) -VS1, -VS2 O (PC Card Memory mode) -VS1, -VS2 (PC Card I/O mode) -VS1, -VS2 (True IDE mode) -WAIT O (PC Card Memory mode) -WAIT (PC Card I/O mode) IORDY (True IDE mode) -WE I (PC Card Memory mode) -WE (PC Card I/O mode) -WE (True IDE mode)
33, 40
These signals are intended to notify VCC requirement to host. -VS1 is held grounded and -VS2 is nonconnected in this card.
42
This signal is active low -WAIT pin. In this card this signal is constantly high level.
This output signal may be used as IORDY. In this card this signal is constantly high impedance. 36 -WE is used for the control of writing register's data in attribute memory area or task file area. -WE is used for the control of writing register's data in attribute memory area. This input signal is not used and should be connected to VCC by the host.
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Signal name Direction Pin No. 24 Description WP is held low because this card does not have write protect switch. -IOIS16 is asserted when task file registers are accessed in 16-bit mode. This output signal is asserted low when this device is expecting a word data transfer cycle. Initial mode is 16-bit. If the user issues a Set Feature Command to put the device in Byte access mode, the card permits 8-bit accesses. WP O (PC Card Memory mode) Write Protect -IOIS16 (PC Card I/O mode) -IOIS16 (True IDE mode)
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Card Block Diagram
VCC GND internal VCC
A0 to A10 -CE1,-CE2 -OE/-ATASEL -WE -IORD -IOWR -REG RESET/-RESET -CSEL D0 to D15 BVD1/-STSCHG/-PDIAG BVD2/-SPKR/-DASP Control signal RDY/-BSY/-IREQ/INTRQ WP/-IOIS16 -INPACK -WAIT/IORDY -VS1 -VS2 -CD1 -CD2 Note: -CE1, -CE2, -OE, -WE, -IORD, -IOWR, -REG, RESET, -CSEL, -PDIAG, -DASP pins are pulled up in card. -CE1, -CE2, -OE, -WE, -IORD, -IOWR, -REG pins are schmitt trigger type input buffer. OPEN Controller Flash memory bus Flash memory Reset IC
X'tal
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Card Function Explanation
Register construction * Attribute region Configuration register * Configuration Option register * Configuration and Status register * Pin Replacement register * Socket and Copy register CIS (C ard Information S tructure) * Task File region Data register Error register Feature register Sector Count register Sector Number register Cylinder Low register Cylinder High register Drive Head register Status register Alternate Status register Command register Device Control register Drive Address register
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Host access specifications 1. Attribute access specifications When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the condition of -REG = "L" as follows. That region can be accessed by Byte/Word/Odd-byte modes which are defined by PC card standard specifications. Attribute Read Access Mode
Mode Standby mode Byte access (8-bit) -REG x L L Word access (16-bit) Odd byte access (8-bit) Note: x: L or H L L -CE2 H H H L L -CE1 H L L L H A0 x L H x x -OE x L L L L -WE x H H H H D8 to D15 High-Z High-Z High-Z invalid invalid D0 to D7 High-Z even byte invalid even byte High-Z
Attribute Write Access Mode
Mode Standby mode Byte access (8-bit) -REG x L L Word access (16-bit) Odd byte access (8-bit) Note: x: L or H L L -CE2 H H H L L -CE1 H L L L H A0 x L H x x -OE x H H H H -WE x L L L L D8 to D15 Don't care Don't care Don't care Don't care Don't care D0 to D7 Don't care even byte Don't care even byte Don't care
Attribute Access Timing Example
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15 read cycle Dout write cycle Din
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2. Task File register access specifications
There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address area. Each case of Task File register read and write operations are executed under the condition as follows. That area can be accessed by Byte/Word/Odd Byte mode which are defined by PC card standard specifications.
(1) I/O address map Task File Register Read Access Mode (1)
Mode Standby mode Byte access (8-bit) -REG -CE2 x L L Word access (16-bit) Note: x: L or H L H H H L L -CE1 H L L L H A0 x L H x x -IORD -IOWR -OE x L L L L x H H H H x H H H H -WE x H H H H D8 to D15 D0 to D7 High-Z High-Z High-Z odd byte odd byte High-Z even byte odd byte even byte High-Z
Odd byte access (8-bit) L
Task File Register Write Access Mode (1)
Mode Standby mode Byte access (8-bit) -REG -CE2 x L L Word access (16-bit) Note: x: L or H L H H H L L -CE1 H L L L H A0 x L H x x -IORD -IOWR -OE x H H H H x L L L L x H H H H -WE x H H H H D8 to D15 D0 to D7 Don't care Don't care Don't care even byte Don't care odd byte odd byte odd byte even byte Don't care
Odd byte access (8-bit) L
Task File Register Access Timing Example (1)
A0 to A10 -REG -CE2/-CE1 -IORD - IOWR D0 to D15 read cycle Dout write cycle Din
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(2) Memory address map Task File Register Read Access Mode (2)
Mode Standby mode Byte access (8-bit) -REG -CE2 x H H Word access (16-bit) Note: x: L or H H H H H L L -CE1 H L L L H A0 x L H x x -OE x L L L L -WE x H H H H -IORD -IOWR D8 to D15 D0 to D7 x H H H H x H H H H High-Z High-Z High-Z odd byte odd byte High-Z even byte odd byte even byte High-Z
Odd byte access (8-bit) H
Task File Register Write Access Mode (2)
Mode Standby mode Byte access (8-bit) -REG -CE2 x H H Word access (16-bit) Note: x: L or H H H H H L L -CE1 H L L L H A0 x L H x x -OE x H H H H -WE x L L L L -IORD -IOWR D8 to D15 D0 to D7 x H H H H x H H H H Don't care Don't care Don't care even byte Don't care odd byte odd byte odd byte even byte Don't care
Odd byte access (8-bit) H
Task File Register Access Timing Example (2)
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15 read cycle Dout write cycle Din
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3. True IDE Mode
The card can be configured in a True IDE mode of operation. This card is configured in this mode only when the -OE input signal is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host.
Only I/O operation to the task file and data register are allowed. If this card is configured during power on sequence, data register are accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature
Command to put the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode Invalid mode Standby mode Data register access Alternate status access Other task file access Note: x: L or H -CE2 L H H L H -CE1 L H L H L A0 to A2 -IORD x x 0 6H 1-7H x x L L L -IOWR x x H H H D8 to D15 D0 to D7 High-Z High-Z odd byte High-Z High-Z High-Z High-Z even byte status out data
True IDE Mode Write I/O Function
Mode Invalid mode Standby mode Data register access Control register access Other task file access Note: x: L or H -CE2 L H H L H -CE1 L H L H L A0 to A2 -IORD x x 0 6H 1-7H x x H H H -IOWR x x L L L D8 to D15 D0 to D7 don't care don't care odd byte don't care don't care don't care don't care even byte control in data
True IDE Mode I/O Access Timing Example
A0 to A2 -CE -IORD -IOWR -IOIS16 D0 to D15 read cycle Dout write cycle Din
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Configuration register specifications This card supports four Configuration registers for the purpose of the configuration and observation of this card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these registers can not be used. 1. Configuration Option register (Address 200H) This register is used for the configuration of the card configuration status and for the issuing soft reset to the card.
bit7 SRESET bit6 LevlREQ bit5 INDEX bit4 bit3 bit2 bit1 bit0
Note: initial value: 00H
Name SRESET (HOST->)
R/W R/W
Function Setting this bit to "1", places the card in the reset state (Card Hard Reset). This operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0", places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) . Card configuration status is reset and the card internal initialized operation starts when Card Hard Reset is executed, so next access to the card should be the same sequence as the power on sequence. This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode interrupt is selected. This bits is used for select operation mode of the card as follows. When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose of Memory card interface recognition.
LevlREQ (HOST->) INDEX (HOST->)
R/W R/W
INDEX bit assignment
INDEX bit 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 1 0 Card mode 0 0 0 Memory card 0 0 1 I/O card 0 1 0 I/O card 0 1 1 I/O card Task File register address 0H to FH, 400H to 7FFH xx0H to xxFH 1F0H to 1F7H, 3F6H to 3F7H 170H to 177H, 376H to 377H Mapping mode memory mapped contiguous I/O mapped primary I/O mapped secondary I/O mapped
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2. Configuration and Status register (Address 202H) This register is used for observing the card state.
bit7 CHGED bit6 SIGCHG bit5 IOIS8 bit4 0 bit3 0 bit2 PWD bit1 INTR bit0 0
Note: initial value: 00H
Name CHGED (CARD->) SIGCHG (HOST->)
R/W R
Function This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to "1" and the card configured for the I/O interface. This bit is set or reset by the host for enabling and disabling the status-change signal (STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept "H". The host sets this field to "1" when it can provide I/O cycles only with on 8-bit data bus (D7 to D0). When this bit is set to "1", the card enters sleep state (Power Down mode). When this bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not become Ready until the power state requested has been entered. This card automatically powers down when it is idle, and powers back up when it receives a command. This bit indicates the internal state of the interrupt request. This bit state is available whether I/O card interface has been configured or not. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero.
R/W
IOIS8 (HOST->) PWD (HOST->)
R/W R/W
INTR (CARD->)
R
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3. Pin Replacement register (Address 204H)
This register is used for providing the signal state of -IREQ signal when the card configured I/O card interface. bit7 0 bit6 0 bit5 bit4 bit3 1 bit2 1 bit1 bit0
CRDY/-BSY 0
RRDY/-BSY 0
Note: initial value: 0CH
Name
R/W
Function This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be written by the host. When read, this bit indicates +READY pin states. When written, this bit is used for CRDY/-BSY bit masking.
CRDY/-BSY R/W (HOST->) RRDY/-BSY R/W (HOST->)
4. Socket and Copy register (Address 206H) This register is used for identification of the card from the other cards. Host can read and write this register. This register should be set by host before this card's Configuration Option register set.
bit7 0 bit6 0 bit5 0 bit4 DRV# bit3 0 bit2 0 bit1 0 bit0 0
Note: initial value: 00H
Name DRV# (HOST->)
R/W R/W
Function This fields are used for the configuration of the plural cards. When host configures the plural cards, written the card's copy number in this field. In this way, host can perform the card's master/slave organization.
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CIS informations CIS informations are defined as follows. By reading attribute address from "0000 H", card CIS informations can be confirmed.
Address Data 7 000H 002H 004H 01H 04H 65 4 3 2 1 0 Description of contents Device info tuple Link length is 4 byte CIS function Tuple code Link to next tuple
CISTPL_DEVICE TPL_LINK
DFH Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed P WPS = 1: No WP S Device speed = 7: ext speed Speed exponent 2k units 400 ns if no wait 2k byte of address space End of device Other conditions device info tuple Link length is 4 bytes VCC MWAIT 3 V, wait is not used Extended speed Device size END marker Tuple code Link to next tuple Other conditions info field
006H 008H 00AH 00CH 00EH 010H 012H
4AH EXT Speed mantissa 01H 1x
FFH List end marker 1CH CISTPL_DEVICE_OC 04H 02H TPL_LINK EXT Reserved
D9H Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed P WPS = 1: No WP S Device speed = 1: 250 ns 2k units 2k byte of address space End of device Device size END marker
014H 016H 018H 01AH 01CH 01EH 020H 022H 024H 026H
01H
1x
FFH List end marker 18H 02H CISTPL_JEDEC_C TPL_LINK
JEDEC ID common memory Tuple code Link length is 2 bytes Link to next tuple JEDEC ID of PC Card ATA
DFH PCMCIA's manufacturer's JEDEC Manufacturer's ID code ID code 01H 20H 04H 07H 00H PCMCIA JEDEC device code CISTPL_MANFID TPL_LINK Low byte of PCMCIA manufacturer's code High byte of PCMCIA manufacturer's code Low byte of product code High byte of product code 2nd byte of JEDEC ID Manufacturer's ID code Link length is 4 bytes HITACHI JEDEC manufacturer's ID
Tuple code Link to next tuple Low byte of manufacturer's ID code
Code of 0 because other byte High byte of manufacturer's is JEDEC 1 byte ID code manufacture's ID HITACHI code for PC CARD Low byte of product code ATA High byte of product code
028H 02AH
00H 00H
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Address Data 7 02CH 02EH 030H 032H 034H 036H 038H 03AH 03CH 03EH 040H 042H 044H 046H 048H 04AH 04CH 04EH 050H 052H 054H 056H 058H 05AH 05CH 05EH 060H 15H 15H 04H 01H 48H 49H 54H 41H 43H 48H 49H 00H 46H 4CH 41H 53H 48H 00H 35H 2EH 30H 00H FFH List end marker 21H 02H 04H 01H CISTPL_FUNCID TPL_LINK TPLFID_FUNCTION = 04H Reserved RP 65 4 3 2 1 0 Description of contents Level 1 version/product info Link length is 15h bytes PCMCIA2.0/JEIDA4.1 PCMCIA2.0/JEIDA4.1 `H' `I' `T' `A' `C' `H' `I' Null terminator `F' `L' `A' `S' `H' Null terminator `5' `.' `0' Null terminator End of device Function ID tuple Link length is 2 bytes END marker Tuple code Link to next tuple Vender specific strings Info string 2 CIS function Tuple code Link to next tuple Major version Minor version Info string 1 CISTPL_VERS_1 TPL_LINK TPPLV1_MAJOR TPPLV1_MINOR
Disk function, may be silicon, PC card function code may be removable R = 0: No BIOS ROM P = 1: Configure card at power on System initialization byte
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Address Data 7 062H 064H 066H 068H 06AH 06CH 06EH 070H 22H 02H 01H 01H 22H 03H 02H 65 4 3 2 1 0 Description of contents Function extension tuple Link length is 2 bytes CIS function Tuple code Link to next tuple Extension tuple type for disk Interface type Tuple code Link to next tuple Extension tuple type for disk Basic ATA option parameters byte 1 CISTPL_FUNCE TPL_LINK
Disk function extension tuple type Disk interface type Disk interface type CISTPL_FUNCE TPL_LINK PC card ATA interface Function extension tuple Link length is 3 bytes
Disk function extension tuple type Single drive DUSV No VPP , silicon, single drive V = 0: No VPP required S = 1: Silicon U = 1: Unique serial # D = 0: Single drive on card
0CH Reserved
072H
0FH R
I
E
N P3 P2 P1 P0
P0: Sleep mode supported Basic ATA option parameters byte 2 P1: Standby mode supported P2: Idle mode suppported P3: Drive auto power control N: Some config excludes 3X7 E: Index bit is emulated I: Twin IOIS16# data reg only R: Reserved Configuration tuple Link length is 5 bytes Tuple code Link to next tuple
074H 076H 078H
1AH CISTPL_CONFIG 05H 01H TPL_LINK RFS RMS RAS
Size of fields byte TPCC_SZ RFS: Reserved RMS: TPCC_RMSK size - 1 = 0 RAS: TPCC_RADR size - 1 = 1 1 byte register mask 2 byte config base address Entry with config index of 03H is final entry in table Configuration registers are located at 200H in REG space Last entry of config registers Location of config registers
07AH 07CH
03H 00H
TPCC_LAST TPCC_RADR (LSB)
07EH 080H
02H
TPCC_RADR (MSB) SPCI I: Configuration index C: Configuration and status P: Pin replacement S: Socket and copy Configuration registers present mask TPCC_RMSK
0FH Reserved
21
HB288256/192/160/128/096/064/032C5
Address Data 7 082H 084H 086H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 8 bytes Memory mapped I/O configuration I = 1: Interface byte follows D = 1: Default entry Configuration index = 0 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVD1 and BVD2 not used IF type = 0: Memory interface CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE_ENTRY 08H TPL_LINK D Configuration index
C0H I
088H
40H
W
RP
B Interface type
Interface description field TPCE_IF
08AH
A1H M
MS
IR IO T P
Feature selection byte M = 1: Misc info present MS = 01: Memory space info TPCE_FS single 2-byte length IR = 0: No interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 5 V VCC nominal value
08CH
01H
R
DI PI AI SI HV LV NV
08EH 090H 092H 094H
55H 08H 00H 20H
X
Mantissa
Exponent
Length in 256 bytes pages (LSB) Length in 256 bytes pages (MSB) X RP RO A T
Length of memory space is 2 Memory space description kB structures (TPCE_MS)
Miscellaneous features field X = 0: No more misc fields TPCE_MI R: Reserved P = 1: Power down supported RO = 0: Not read only mode A = 0: Audio not supported T = 0: Single drive
22
HB288256/192/160/128/096/064/032C5
Address Data 7 096H 098H 09AH 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 6 bytes Memory mapped I/O configuration I = 0: No Interface byte D = 0: No Default entry Configuration index = 0 CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE_ENTRY 06H 00H TPL_LINK I D Configuration index
09CH
01H
M
MS
IR IO T P
Feature selection byte M = 0: No Misc info MS = 00: No Memory space TPCE_FS info IR = 0: No interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 3.0 V +0.3 V VCC nominal value Extension byte
09EH
21H
R
DI PI AI SI HV LV NV
0A0H 0A2H 0A4H
B5H X 1EH X 4DH X
Mantissa Extension Mantissa
Exponent
Exponent
Max average current over 10 Max. average current msec is 45 mA
23
HB288256/192/160/128/096/064/032C5
Address Data 7 0A6H 0A8H 0AAH 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 10 bytes CIS function Tuple code Link to next tuple 1BH CISTPL_CFTABLE_ENTRY 0AH TPL_LINK C1H I D Configuration INDEX
Contiguous I/O mapped ATA Configuration table index byte TPCE_INDX registers configuration I = 1: Interface byte follows D = 1: Default entry Configuration index = 1 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVS1 and BVD2 not used IF type = 1: I/O interface Interface description field TPCE_IF
0ACH
41H
W
RP
B Interface type
0AEH
99H
M
MS
IR IO T P
M = 1: Misc info present Feature selection byte MS = 00: No memory space TPCE_FS info IR = 1: Interrupt info present IO = 1: I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down Current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 5 V VCC nominal value
0B0H
01H
R
DI PI AI SI HV LV NV
0B2H 0B4H
55H 64H
X R
Mantissa SE
Exponent
IO AddrLine
S = 1: 16-bit hosts supported I/O space description field E = 1: 8-bit hosts supported TPCE_IO IO AddrLine: 4 lines decoded N Interrupt request description S = 1: Share logic active structure P = 1: Pulse mode IRQ TPCE_IR supported L = 1: Level mode IRQ supported M = 1: Bit mask of IRQs present V = 0: No vender unique IRQ B = 0: No bus error IRQ I = 0: No IO check IRQ N = 0: No NMI
0B6H
F0H S
PL
MVBI
24
HB288256/192/160/128/096/064/032C5
Address Data 7 0B8H 65 4 3 2 1 0 Description of contents CIS function FFH IRQ IR IR IR IR IR IR IRQ0 7 QQQQQQ 654321 FFH IRQ IR IR IR IR IR IR IRQ8 15 Q Q Q Q Q Q 14 13 12 11 10 9 20H X RP RO A T IRQ level to be routed 0 to 15 Mask extension byte 1 recommended TPCE_IR Recommended routing to any Maskextension byte 2 "normal, maskable" IRQ. TPCE_IR Miscellaneous features field X = 0: Nomore misc fields TPCE_MI R: reserved P = 1: Power down supported RO = 0: Not read only mode A = 0: Audio not supported T = 0: Single drive
0BAH
0BCH
25
HB288256/192/160/128/096/064/032C5
Address Data 7 0BEH 0C0H 0C2H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 6 bytes CIS function Tuple code Link to next tuple 1BH CISTPL_CFTABLE_ENTRY 06H 01H TPL_LINK I D Configuration index
Contiguous I/O mapped ATA Configuration table index byte registers configuration TPCE_INDX I = 0: No Interface byte D = 0: No Default entry Configuration index = 1 Feature selection byte M = 0: No Misc info MS = 00: No Memory space TPCE_FS info IR = 0: No interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 3.0 V +0.3 V VCC nominal value Extension byte
0C4H
01H
M
MS
IR IO T P
0C6H
21H
R
DI PI AI SI HV LV NV
0C8H 0CAH 0CCH
B5H X 1EH X 4DH X
Mantissa Extension Mantissa
Exponent
Exponent
Max average current over 10 Max. average current msec is 45 mA
26
HB288256/192/160/128/096/064/032C5
Address Data 7 0CEH 0D0H 0D2H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 15 bytes ATA primary I/O mapped configuration I = 1: Interface byte follows D = 1: default entry follows Configuration index = 2 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVS1 and BVD2 not used IF type = 1: I/O interface CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE_ENTRY 0FH TPL_LINK C2H I D Configuration INDEX
0D4H
41H
W
RP
B Interface type
Interface description field TPCE_IF
0D6H
99H
M
MS
IR IO T P
M = 1: misc info present Feature selection byte MS = 00: No memory space TPCE_FS info IR = 1: Interrupt info present IO = 1: I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down Current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 5 V VCC nominal value
0D8H
01H
R
DI PI AI SI HV LV NV
0DAH 0DCH
55H
X
Mantissa SE
Exponent
EAH R
IO AddrLine
I/O space description field R = 1: Range follows S = 1: 16-bit hosts supported TPCE_IO E = 1: 8-bit hosts supported IO AddrLines: 10 lines decoded LS = 1: Size of lengths is 1 I/O range format description byte AS = 2: Size of address is 2 bytes N Range = 1: Address range - 1
0DEH
61H
LS
AS
N range
27
HB288256/192/160/128/096/064/032C5
Address Data 7 0E0H 0E2H 0E4H 0E6H 0E8H 0EAH 0ECH F0H 01H 07H F6H 03H 01H EEH S PL M IRQ level 65 4 3 2 1 0 Description of contents 1st I/O base address (LSB) 1st I/O base address (MSB) 1st I/O length - 1 2nd I/O base address (LSB) 2nd I/O base address (MSB) 2nd I/O length - 1 S = 1: Share logic active P = 1: Pulse mode IRQ supported L = 1: Level mode IRQ supported M = 0: Bit mask of IRQs present IRQ level is IRQ14 2nd I/O range length Interrupt request description structure TPCE_IR 1st I/O range length 2nd I/O range address CIS function 1st I/O range address
0EEH
20H
X
RP
RO A T
Miscellaneous features field X = 0: Nomore misc fields TPCE_MI R: reserved P = 1: Power down supported RO = 0: Not read only mode A = 0: Audio not supported T = 0: Single drive
28
HB288256/192/160/128/096/064/032C5
Address Data 7 0F0H 0F2H 0F4H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 6 bytes ATA primary I/O mapped configuration I = 0: No Interface byte D = 0: No Default entry Configuration index = 2 CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE_ENTRY 06H 02H TPL_LINK I D Configuration index
0F6H
01H
M
MS
IR IO T P
Feature selection byte M = 0: No Misc info MS = 00: No Memory space TPCE_FS info IR = 0: No interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 3.0 V +0.3 V VCC nominal value Extension byte
0F8H
21H
R
DI PI AI SI HV LV NV
0FAH 0FCH 0FEH
B5H X 1EH X 4DH X
Mantissa Extension Mantissa
Exponent
Exponent
Max average current over 10 Max. average current msec is 45 mA
29
HB288256/192/160/128/096/064/032C5
Address Data 7 100H 102H 104H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 15 bytes ATA secondary I/O mapped configuration I = 1: Interface byte follows D = 1: default entry Configuration index = 3 W = 0: Wait not used R = 1: Ready active P = 0: WP not used B = 0: BVS1 and BVD2 not used IF type = 1: I/O interface CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE_ENTRY 0FH TPL_LINK C3H I D Configuration INDEX
106H
41H
W
RP
B Interface type
Interface description field TPCE_IF
108H
99H
M
MS
IR IO T P
M = 1: misc info present Feature selection byte MS = 00: No memory space TPCE_FS info IR = 1: Interrupt info present IO = 1: I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down Current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 5 V VCC nominal value
10AH
01H
R
DI PI AI SI HV LV NV
10CH 10EH
55H
X
Mantissa SE
Exponent
EAH R
IO AddrLine
I/O space description field R = 1: Range follows S = 1: 16-bit hosts supported TPCE_IO E = 1: 8-bit hosts supported IO AddrLines: 10 lines decoded LS = 1: Size of lengths is 1 I/O range format description byte AS = 2: Size of address is 2 bytes N Range = 1: Address range - 1
110H
61H
LS
AS
N range
30
HB288256/192/160/128/096/064/032C5
Address Data 7 112H 114H 116H 118H 11AH 11CH 11EH 70H 01H 07H 76H 03H 01H EEH S PL M IRQ level 65 4 3 2 1 0 Description of contents 1st I/O base address (LSB) 1st I/O base address (MSB) 1st I/O length - 1 2nd I/O base address (LSB) 2nd I/O base address (MSB) 2nd I/O length - 1 S = 1: Share logic active P = 1: Pulse mode IRQ supported L = 1: Level mode IRQ supported M = 0: Bit mask of IRQs present IRQ level is IRQ14 2nd I/O range length Interrupt request description structure TPCE_IR 1st I/O range length 2nd I/O range address CIS function 1st I/O range address
120H
20H
X
RP
RO A T
Miscellaneous features field X = 0: Nomore misc fields TPCE_MI R: reserved P = 1: Power down supported RO = 0: Not read only mode A = 0: Audio not supported T = 0: Single drive
31
HB288256/192/160/128/096/064/032C5
Address Data 7 122H 124H 126H 65 4 3 2 1 0 Description of contents Configuration table entry tuple Link length is 6 bytes ATA secondary I/O mapped configuration I = 0: No Interface byte D = 0: No Default entry Configuration index = 3 CIS function Tuple code Link to next tuple Configuration table index byte TPCE_INDX 1BH CISTPL_CFTABLE_ENTRY 06H 03H TPL_LINK I D Configuration index
128H
01H
M
MS
IR IO T P
Feature selection byte M = 0: No Misc info MS = 00: No Memory space TPCE_FS info IR = 0: No interrupt info present IO = 0: No I/O port info present T = 0: No timing info present P = 1: VCC only info Nominal voltage only follows Power parameters for VCC R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Nominal voltage = 3.0 V +0.3 V VCC nominal value Extension byte
12AH
21H
R
DI PI AI SI HV LV NV
12CH 12EH 130H 132H 134H 136H
B5H X 1EH X 4DH X 14H 00H
Mantissa Extension Mantissa
Exponent
Exponent
Max average current over 10 Max. average current msec is 45 mA No link control tuple Link is 0 bytes End of list tuple Tuple code Link to next tuple Tuple code
CISTPL_NO_LINK
FFH CISTPL_END
32
HB288256/192/160/128/096/064/032C5
Task File register specification These registers are used for reading and writing the storage data in this card. These registers are mapped five types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as follows.
Memory map (INDEX = 0) -REG A10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A9 to A4 A3 x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 x x A2 0 0 0 0 1 1 1 1 0 0 1 1 1 x x A1 0 0 1 1 0 0 1 1 0 0 0 1 1 x x A0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH 8H 9H -OE = L Data register Error register Sector count register -WE = L Data register Feature register Sector count register
Sector number register Sector number register Cylinder low register Cylinder high register Drive head register Status register Cylinder low register Cylinder high register Drive head register Command register
Dup. even data register Dup. even data register Dup. odd data register Dup. error register Alt. status register Drive address register Even data register Odd data register Dup. odd data register Dup. feature register Device control register Reserved Even data register Odd data register
33
HB288256/192/160/128/096/064/032C5
Contiguous I/O map (INDEX = 1) -REG A10 to A4 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register
Dup. even data register Dup. even data register Dup. odd data register Dup. error register Alt. status register Drive address register Dup. odd data register Dup. feature register Device control register Reserved
Primary I/O map (INDEX = 2) -REG A10 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x A9 to A4 1FH 1FH 1FH 1FH 1FH 1FH 1FH 1FH 3FH 3FH A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
34
HB288256/192/160/128/096/064/032C5
Secondary I/O map (INDEX = 3) -REG A10 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x A9 to A4 17H 17H 17H 17H 17H 17H 17H 17H 37H 37H A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
True IDE Mode I/O map -CE2 1 1 1 1 1 1 1 1 0 0 -CE1 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD = L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR = L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
35
HB288256/192/160/128/096/064/032C5
1. Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. This register can be accessed in word mode and byte mode. This register overlaps the Error or Feature register.
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D0 to D15
2. Error register: This register is a read only register, and it is used for analyzing the error content at the card accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set to "0" (Ready).
bit7 BBK bit6 UNC bit5 "0" bit4 IDNF bit3 "0" bit2 ABRT bit1 "0" bit0 AMNF
bit 7 6 4 2 0
Name BBK (Bad BlocK detected) UNC (Data ECC error) IDNF (ID Not Found) ABRT (ABoRTed command)
Function This bit is set when a Bad Block is detected in requested ID field. This bit is set when Uncorrectable error is occurred at reading the card. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of the card status condition. (Not ready, Write fault, Invalid command, etc.)
AMNF (Address Mark Not Found) This bit is set in case of a general error.
3. Feature register: This register is a write only register, and provides information regarding features of the drive which the host wishes to utilize.
bit7 bit6 bit5 bit4 bit3 Feature byte bit2 bit1 bit0
4. Sector count register: This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. If the value of this register is zero, a count of 256 sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request. This register's initial value is "01H".
bit7 bit6 bit5 bit4 bit3 Sector count byte bit2 bit1 bit0
36
HB288256/192/160/128/096/064/032C5
5. Sector number register: This register contains the starting sector number which is started by following sector transfer command.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Sector number byte
6. Cylinder low register: This register contains the low 8-bit of the starting cylinder address which is started by following sector transfer command.
bit7 bit6 bit5 bit4 bit3 Cylinder low byte bit2 bit1 bit0
7. Cylinder high register: This register contains the high 8-bit of the starting cylinder address which is started by following sector transfer command.
bit7 bit6 bit5 bit4 bit3 Cylinder high byte bit2 bit1 bit0
8. Drive head register: This register is used for selecting the Drive number and head number for the following command.
bit7 1 bit6 LBA bit5 1 bit4 DRV bit3 Head number bit2 bit1 bit0
Note: DRV: Drive number Head number: Head number
bit 7 6
Name 1 LBA
Function This bit is set to "1". LBA is a flag to select either Cylinder / Head / Sector (CHS) or Logical Block Address (LBA) mode. When LBA = 0, CHS mode is selected. When LBA = 1, LBA mode is selected. In LBA mode, the Logical Block Address is interrupted as follows: LBA07 - LBA00: Sector Number Register D7 - D0. LBA15 - LBA08: Cylinder Low Register D7 - D0. LBA23 - LBA16: Cylinder High Register D7 - D0. LBA27 - LBA24: Drive / Head Register bits HS3 - HS0. This bit is set to "1". This bit is used for selecting the Master (Card 0) and Slave (Card 1) in Master/Slave organization. The card is set to be Card 0 or 1 by using DRV# of the Socket and Copy register. This bit is used for selecting the Head number for the following command. Bit 3 is MSB.
5 4
1 DRV (DRiVe select)
3 to 0 Head number
37
HB288256/192/160/128/096/064/032C5
9. Status register: This register is read only register, and it indicates the card status of command execution. When this register is read in configured I/O card mode (INDEX = 1, 2, 3) and level interrupt mode, -IREQ is negated. This register should be accessed in byte mode. In word mode, it is recommended that Alternate status register may be used as this register.
bit7 BSY bit6 DRDY bit5 DWF bit4 DSC bit3 DRQ bit2 CORR bit1 IDX bit0 ERR
bit 7 6
Name BSY (BuSY) DRDY (Drive ReaDY)
Function This bit is set when the card internal operation is executing. When this bit is set to "1", other bits in this register are invalid. If this bit and DSC bit are set to "1", the card is capable of receiving the read or write or seek requests. If this bit is set to "0", the card prohibits these requests. This bit is set if this card indicates the write fault status. This bit is set when the drive seek complete. This bit is set when the information can be transferred between the host and Data register. This bit is cleared when the card receives the other command. This bit is set when a correctable data error has been occurred and the data has been corrected. This bit is always set to "0". This bit is set when the previous command has ended in some type of error. The error information is set in the other Status register or Error register. This bit is cleared by the next command.
5 4 3
DWF (Drive Write Fault) DSC (Drive Seek Complete) DRQ (Data ReQuest)
2 1 0
CORR (CORRected data) IDX (InDeX) ERR (ERRor)
10. Alternate status register: This register is the same as Status register in physically, so the bit assignment refers to previous item of Status register. But this register is different from Status register that -IREQ is not negated when data read. 11. Command register: This register is write only register, and it is used for writing the command at executing the drive operation. The command code written in the command register, after the parameter is written in the Task File during the card is Ready state.
38
HB288256/192/160/128/096/064/032C5
Used parameter Command Check power mode Execute drive diagnostic Erase sector Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector Read verify sector Recalibrate Request sense Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Translate sector Wear level Write buffer Write long sector Write multiple Write multiple w/o erase Write sector Write sector w/o erase Write verify Command code E5H or 98H 90H C0H 50H ECH E3H or 97H E1H or 95H 91H E4H C4H 22H or 23H 20H or 21H 40H or 41H 1XH 03H 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H 87H F5H E8H 32H or 33H C5H CDH 30H or 31H 38H 3CH FR N N N N N N N N N N N N N N N N Y N N N N N N N N N N N N N SC N N Y Y N Y N Y N Y N Y Y N N N N Y N N N Y N N N Y Y Y Y Y SN N N Y N N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y CY N N Y Y N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD N N Y Y N N N Y N Y Y Y Y N N Y N N N N N Y Y N Y Y Y Y Y Y LBA N N Y Y N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y
39
HB288256/192/160/128/096/064/032C5
Note: FR: Feature register SC: Sector Count register SN: Sector Number register CY: Cylinder register DR: DRV bit of Drive Head register HD: Head Number of Drive Head register LBA: Logical Block Address Mode Supported Y: The register contains a valid parameter for this command. N: The register does not contain a valid parameter for this command.
40
HB288256/192/160/128/096/064/032C5
12. Device control register: This register is write only register, and it is used for controlling the card interrupt request and issuing an ATA soft reset to the card.
bit7 x bit6 x bit5 x bit4 x bit3 1 bit2 SRST bit1 nIEN bit0 0
bit
Name
Function don't care This bit is set to "1". This bit is set to "1" in order to force the card to perform Task File Reset operation. This does not change the Card Configuration registers as a Hardware Reset does. The card remains in Reset until this bit is reset to "0". This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ is enabled. When this bit is set to "1", -IREQ is disabled. This bit is set to "0".
7 to 4 x 3 2 1 SRST (Software ReSeT)
1 0
nIEN (Interrupt ENable) 0
13. Drive Address register: This register is read only register, and it is used for confirming the drive status. This register is provides for compatibility with the AT disk drive interface. It is recommended that this register is not mapped into the host's I/O space because of potential conflicts on bit7.
bit7 x bit6 nWTG bit5 nHS3 bit4 nHS2 bit3 nHS1 bit2 nHS0 bit1 nDS1 bit0 nDS0
bit 7 6
Name x nWTG (WriTing Gate)
Function This bit is unknown. This bit is unknown. These bits is the negative value of Head Select bits (bit 3 to 0) in Drive/Head register. This bit is unknown. This bit is unknown.
5 to 2 nHS3-0 (Head Select3-0) 1 0 nDS1 (Idrive Select1) nDS0 (Idrive Select0)
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HB288256/192/160/128/096/064/032C5
ATA Command specifications This table summarizes the ATA command set with the paragraphs. Following shows the support commands and command codes which are written in command registers. ATA Command Set
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Command set Check power mode Execute drive diagnostic Erase sector(s) Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector (s) Read verify sector (s) Recalibrate Request sense Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Translate sector Wear level Write buffer Write long sector Write multiple Write multiple w/o erase Write sector Write sector(s) w/o erase Write verify Code E5H or 98H 90H C0H 50H ECH E3H or 97H E1H or 95H 91H E4H C4H 22H, 23H 20H, 21H 40H, 41H 1XH 03H 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H 87H F5H E8H 32H or 33H C5H CDH 30H or 31H 38H 3CH FR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- -- -- -- -- -- -- -- -- -- -- -- SC -- -- Y Y -- Y -- Y -- Y -- Y Y -- -- -- -- Y -- -- -- Y -- -- -- Y Y Y Y Y SN -- -- Y -- -- -- -- -- -- Y Y Y Y -- -- Y -- -- -- -- -- Y -- -- Y Y Y Y Y Y CY -- -- Y Y -- -- -- -- -- Y Y Y Y -- -- Y -- -- -- -- -- Y -- -- Y Y Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD -- -- Y Y -- -- -- Y -- Y Y Y Y -- -- Y -- -- -- -- -- Y Y -- Y Y Y Y Y Y LBA -- -- Y Y -- -- -- -- -- Y Y Y Y -- -- Y -- -- -- -- -- Y -- -- Y Y Y Y Y Y
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Note: FR: Feature Register SC: Sector Count register (00H to FFH) SN: Sector Number register (01H to 20H) CY: Cylinder Low/High register (to) DR: Drive bit of Drive/Head register HD: Head No.(0 to 3) of Drive/Head register NH: No. of Heads Y: Set up --: Not set up
1. Check Power Mode (code: E5H or 98H): This command checks the power mode. 2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests implemented by the Card. 3. Erase Sector(s) (code: C0H): This command is used to erase data sectors. 4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive. But selected sector data is not exchange. This card excepts a sector buffer of data from the host to follow the command with same protocol as the Write Sector command. 5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the Card.
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Identify Drive Information
Word address Default value Total bytes 0 1 2 3 4 5 6 7 to 8 9 10 to 19 20 21 22 23 to 46 47 48 49 50 51 52 53 to 58 59 60 to 61 62 to 255 848AH XXXX 0000H 00XXH 0000H XXXX XXXX XXXX 0000H XXXX 0002H 0002H 0004H XXXX 0001H 0000H 0200H 0000H 0100H 0000H XXXX 010XH XXXX 0000H 2 2 2 2 2 2 2 4 2 20 2 2 2 48 2 2 2 2 2 2 12 2 4 388 Data field type information General configuration bit-significant information Default number of cylinders Reserved Default number of heads Number of unformatted bytes per track Number of unformatted bytes per sector Default number of sectors per track Number of sectors per card (Word7 = MSW, Word8 = LSW ) Reserved Reserved Buffer type (dual ported) Buffer size in 512 byte increments # of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII etc. Maximum of 1 sector on Read/Write Multiple command Double Word not supported Capabilities: DMA NOT Supported (bit8), LBA supported (bit9) Reserved PIO data transfer cycle timing mode 1 DMA data transfer cycle timing mode not Supported Reserved Multiple sector setting is valid Total number of sectors addressable in LBA Mode Reserved
6. Idle (code: E3H or 97H): This command causes the PC Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. 7. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle (Read) mode, clear BSY and generate an interrupt. 8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per track and the number of heads per cylinder. 9. Read Buffer (code: E4H): This command enables the host to read the current contents of the PC card's sector buffer.
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10. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. 11. Read Long Sector (code: 22H or 23H): This command performs similarly to the Read Sector(s) command except that it returns 516 bytes of data instead of 512 bytes. 12. Read Sector(s) (code: 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. 13. Read Verify Sector(s) (code: 40H or 41H): This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host . 14. Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided for compatibility purposes. 15. Request Sense (code: 03H): This command requests an extended error code after command ends with an error. 16. Seek (code: 7XH): This command is effectively a NOP command to the Card although it does perform a range check. 17. Set Features (code: EFH): This command is used by the host to establish or select certain features.
Feature 01H 55H 66H 81H BBH CCH Operation Enable 8-bit data transfers. Disable Read Look Ahead. Disable Power on Reset(POR) establishment of defaults at Soft Reset. Disable 8-bit data transfer. 4bytes of data apply on Read/Write Long commands. Enable Power on Reset(POR) establishment of default at Soft Reset.
18. Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple operations and establishes the block count for these commands. 19. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. 20. Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. 21. Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep mode(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.
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22. Translate Sector (code: 87H): This card does not support by this command the function of determining the exact number of times a user sector has been erased and programmed because this card always responds with "00H", though this command could provide information containing the desired cylinder, head and sector, including its Logical Address, etc. 23. Wear level (code: F5H): This command is effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with an 00H indicating Wear Level is not needed. 24. Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card's sector buffer with any data pattern desired. 25. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. 26. Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple command. 27. Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. 28. Write Sector(s) (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. 29. Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. 30. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written.
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Sector Transfer Protocol 1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.
Start Set the cylinder low / high register
I/O Access, INDEX=1
Set the head No. of drive head register (1)Set the logical sector number Set the sector number register Set "01H" in sector count register
Set "20H" in Command register
(2)
Read the status register (3) N "58H"? Y Read 256 times the data register (512 bytes) (4)Burst data transfer
Read the status register N (5) "50H"? Y Wait the command input
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(1) A0 to A10 -CE1 -CE2 -IOWR -IORD D0 to D15 -IREQ 01H20H 80H 58H Data transfer 80H 50H (2) 7H (3) 7H 0H (4) 0H (5) 7H 7H
4H 5H 6H 3H 2H 7H
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2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows.
Start Set the cylinder low / high register
I/O Access, INDEX=1
Set the head No. of drive head register (1) Set the logical sector number Set the sector number register Set "01H" in sector count register
Set "30H" in command register
(2)
Read the status register (3) N "58H"? Y Write 256 times the data register (512 bytes) (4) Burst data transfer
Read the status register N (5) "50H"? Y Wait the command input
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(1) A0 to A10 -CE1 -CE2 -IOWR -IORD D0 to D15 -IREQ 01H30H 80H 58H Data transfer 80H 50H (2) 7H (3) 7H 0H (4) 0H 7H (5) 7H
4H 5H 6H 3H 2H 7H
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Absolute Maximum Ratings
Parameter All input/output voltages VCC voltage Operating temperature range Storage temperature range Note: Symbol Vin, Vout VCC Topr Tstg Value -0.3 to VCC + 0.3 -0.3 to +6.5 0 to +60 -20 to +65 Unit V V C C Note 1
1. Vin, Vout min = -2.0 V for pulse width 20 ns.
Recommended Operating Conditions
Parameter Operating temperature VCC voltage Symbol Ta VCC Min 0 4.5 3.15 Typ 25 5.0 3.3 Max 60 5.5 3.45 Unit C V V
Capacitance (Ta = 25C, f = 1MHz)
Parameter Input capacitance Output capacitance Symbol Cin Cout Min -- -- Typ -- -- Max 35 35 Unit pF pF Test conditions Vin = 0 V Vout = 0 V
System Performance
Item Set up times (Reset to ready) Set up times (Sleep to idle) Data transfer rate to/from host Controller overhead (Command to DRQ) Data transfer cycle end to ready (Sector write) Performance 100 ms (max) 2 ms (max) 8 MB/s burst 2 ms (max) 2 ms (typ)
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DC Characteristics-1 (Ta = 0 to +60C, VCC = 5 V 10%, 3.3 V 5%)
Parameter Input leakage current Output voltage Symbol I LI VOL VOH Note: Min -- -- Typ -- -- Max 1 0.4 -- Unit A V V Test conditions Vin = GND to VCC I OL = 8 mA I OH = -8 mA Note 1
VCC - 0.8 --
1. Except pulled up input pin.
3.3 V Parameter Input voltage (CMOS) Symbol Min VIL VIH Input voltage VIL (Schmitt trigger) VIH -- 2.4 -- -- Typ -- -- 1.0 1.8 Max 0.6 -- -- --
5V Min -- 4.0 -- -- Typ -- -- 2.0 2.8 Max 0.8 -- -- -- Unit Test conditions V V V V
DC Characteristics-2 (Ta = 0 to +60C, VCC = 5.0 V 10%)
32MB/64MB/ 96MB/ 160MB/192 128MB MB/256MB/ Parameter Sleep/standby current Symbol I SP1 Typ 0.5 Max 1.0 Typ 0.7 Max 1.5 Unit Test conditions mA CMOS level (control signal = VCC - 0.2 V) (In Memory card mode and I/O card mode) CMOS level (control signal = VCC - 0.2 V) during sector read transfer
Sector read current I CCR (DC)
40
75 120 75 120
40 80 45 80
75 120 75 120
mA mA mA mA
I CCR (Peak) 80 Sector write current I CCW (DC) 45
CMOS level (control signal = VCC - 0.2 V) during sector write transfer
I CCW (Peak) 80
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DC Characteristics-3 (Ta = 0 to +60C, VCC = 3.3 V 5%)
32MB/64MB/ 96MB/ 160MB/192 128MB MB/256MB Parameter Sleep/standby current Symbol I SP1 Typ 0.3 Max 1.0 Typ 0.4 Max 1.5 Unit Test conditions mA CMOS level (control signal = VCC - 0.2 V) (In Memory card mode and I/O card mode) CMOS level (control signal = VCC - 0.2 V) during sector read transfer
Sector read current I CCR (DC)
25
50 80 50 100
25 50 25 50
50 80 50 100
mA mA mA mA
I CCR (Peak) 50 Sector write current I CCW (DC) 25
CMOS level (control signal = VCC - 0.2 V) during sector write transfer
I CCW (Peak) 50
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DC Current Waveform (VCC = 5 V, Ta = 25C)
Power on Operation (Reference only)
Current
DC Time Power on
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Sector Read
Current
ICCR(Peak)
ICCR(DC) 0 Time Command write Complete of sector read
Sector Write
Current
ICCW(Peak)
ICCW(DC) 0 Time Command write Complete of sector write
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AC Characteristics (Ta = 0 to +60C, VCC = 5 V 10%, 3.3 V 5%)
Attribute Memory Read AC Characteristics
250 ns Parameter Read cycle time Address access time -CE access time -OE access time Output disable time (-CE) Output disable time (-OE) Output enable time (-CE) Output enable time (-OE) Data valid time (A) Address setup time Address hold time -CE setup time -CE hold time Symbol tCR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) tsu(A) th(A) Min 250 -- -- -- -- -- 5 5 0 30 20 0 20 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- 250 250 125 100 100 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(CE) th(CE)
Attribute Memory Read Timing
tCR A0 to A10 -REG ta(A) ta(CE) -CE2/-CE1 tsu(A) -OE ten(OE) ten(CE) D0 to D15 Valid Output -WE, -IOWR, -IORD : High Fix tdis(OE) tsu(CE) ta(OE) th(CE) tdis(CE) th(A) tv(A)
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Attribute Memory Write AC Characteristics
250 ns Parameter Write cycle time Write pulse time Address setup time Address setup time (-WE) -CE setup time (-WE) Data setup time (-WE) Data hold time Write recover time Output disable time (-WE) Output disable time (-OE) Output enable time (-WE) Output enable time (-OE) Output enable setup time (-WE) Output enable hold time (-WE) -CE setup time -CE hold time Symbol tCW tw(WE) tsu(A) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE) tsu(OE-WE) th(OE-WE) Min 250 150 30 180 180 80 30 30 -- -- 5 5 10 10 0 20 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- 100 100 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(CE) th(CE)
Attribute Memory Write Timing
tCW A0 to A10 -REG tsu(CE-WEH) -CE2/-CE1 -OE tsu(A) -WE D0 to D15(Din) tdis(OE) D0 to D15(Dout) ten(WE) -IOWR, -IORD : High Fix tdis(WE) tsu(OE-WE) tw(WE) tsu(D-WEH) Input Data ten(OE) trec(WE) th(OE-WE) th(D) tsu(A-WEH) tsu(CE) th(CE)
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I/O Access Read AC Characteristics
Parameter Data delay after -IORD Data hold following -IORD -IORD pulse width Address setup before -IORD Address hold following -IORD -CE setup before -IORD -CE hold following -IORD -REG setup before -IORD -REG hold following -IORD -INPACK delay falling from -IORD -INPACK delay rising from -IORD -IOIS16 delay falling from address -IOIS16 delay rising from address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) Min -- 0 165 70 20 5 20 5 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 100 -- -- -- -- -- -- -- -- 45 45 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tdfINPACK(IORD) 0 tdrINPACK(IORD) -- tdfIOIS16(ADR) tdrIOIS16(ADR) -- --
I/O Access Read Timing
A0 to A10 thA(IORD) tsuREG(IORD) thREG(IORD) -REG tsuCE(IORD) -CE2/-CE1 tw(IORD) -IORD tsuA(IORD) -INPACK tdfIOIS16(ADR) tdfINPACK(IORD) -IOIS16 th(IORD) D0 to D15 td(IORD) -WE, -OE, -IOWR : High Fix
Valid Output
thCE(IORD)
tdrINPACK(IORD)
tdrIOIS16(ADR)
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HB288256/192/160/128/096/064/032C5
I/O Access Write AC Characteristics
Parameter Data setup before -IOWR Data hold following -IOWR -IOWR pulse width Address setup before -IOWR Address hold following -IOWR -CE setup before -IOWR -CE hold following -IOWR -REG setup before -IOWR -REG hold following -IOWR -IOIS16 delay falling from address -IOIS16 delay rising from address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) Min 60 30 165 70 20 5 20 5 0 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns
I/O Access Write Timing
A0 to A10 thA(IOWR) tsuREG(IOWR) thREG(IOWR) -REG tsuCE(IOWR) -CE2/-CE1 tsuA(IOWR) tw(IOWR) -IOWR tdfIOIS16(ADR) -IOIS16 tsu(IOWR) D0 to D15 Data In -WE, -OE, -IORD : High Fix th(IOWR) tdrIOIS16(ADR) thCE(IOWR)
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Common Memory Access Read AC Characteristics
Parameter -CE access time Output disable time (-OE) Address setup time Address hold time -CE setup time -CE hold time Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) Min -- -- 30 20 0 20 Typ -- -- -- -- -- -- Max 125 100 -- -- -- -- Unit ns ns ns ns ns ns
Common Access Read Timing
A0 to A10 tsu(A) -REG -CE2/-CE1 tsu(CE) ta(OE) -OE tdis(OE) D0 to D15
Valid Output
th(A)
th(CE)
-WE, -IORD, -IOWR : High Fix
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HB288256/192/160/128/096/064/032C5
Common Memory Access Write AC Characteristics
Parameter Data setup time (-WE) Data hold time Write pulse time Address setup time -CE setup time Write recover time -CE hold following -WE Symbol tsu(D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(CE) Min 80 30 150 30 0 30 20 Typ -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
Common Access Write Timing
A0 to A10 -REG tsu(CE) -CE2/-CE1 tsu(A) -WE tw(WE) tsu(D-WEH) D0 to D15 th(D) th(CE)
trec(WE)
Data In
-IOWR, -IORD, -OE : High Fix
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HB288256/192/160/128/096/064/032C5
True IDE Mode Access Read AC Characteristics
Parameter data delay after IORD data hold following IORD IORD width time address setup before IORD address hold following IORD CE setup before IORD CE hold following IORD IOIS16 delay falling from address IOIS16 delay rising from address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) Min -- 0 165 70 20 5 20 -- -- Typ -- -- -- -- -- -- -- -- -- Max 100 -- -- -- -- -- -- 35 35 Unit ns ns ns ns ns ns ns ns ns
True IDE Mode Access Read Timing
A0 to A2 tsuA(IORD) -CE2/-CE1 -IORD td(IORD) -IOIS16 tdflOIS16(ADR) th(IORD) D0 to D15
Valid Output
tsuCE(IORD)
thA(IORD) thCE(IORD) tw(IORD)
tdrlOIS16(ADR)
-IOWR: High Fix, -OE: Low Fix, -WE: High Fix, A3 to A10: GND
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HB288256/192/160/128/096/064/032C5
True IDE Mode Access Write AC Characteristics
Parameter Data setup before IOWR data hold following IOWR IORD width time address setup before IOWR address hold following IOWR CE setup before IOWR CE hold following IOWR IOIS16 delay falling from address IOIS16 delay rising from address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) Min 60 30 165 70 20 5 20 -- -- Typ -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 35 35 Unit ns ns ns ns ns ns ns ns ns
True IDE Mode Access Write Timing
A0 to A2 tsuA(IOWR) -CE2/-CE1 -IOWR tdrlOIS16(ADR) -IOIS16 tdflOIS16(ADR) D0 to D15 tsu(IOWR) th(IOWR)
Valid Output
tsuCE(IOWR)
thA(IOWR) thCE(IOWR) tw(IOWR)
-IORD: High Fix, -OE: Low Fix, -WE: High Fix, A3 to A10: GND
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Reset Characteristics (only Memory Card Mode or I/O Card Mode) Hard Reset Characteristics
Parameter Reset setup time -CE recover time VCC rising up time VCC falling down time Reset pulse width Symbol tsu(RESET) trec(VCC) tpr tpf tw(RESET) Min 100 1 0.1 3 10 Typ -- -- -- -- -- -- -- Max -- -- 100 300 -- -- -- Unit ms s ms ms s ms ms 1 Test conditions Note
th(Hi-ZRESET) 1 ts(Hi-ZRESET) 100 Note:
1. As for this specification, it is fitted activity state when change. When reset signal is non-activity state and a card is ready state, can shift to power supply cutoff sequence instantly.
Hard Reset Timing
tpr 90% Vcc 10% 90% trec(Vcc) 10% tpf
-CE1, -CE2 th(Hi-ZRESET) High-Z tsu(RESET) tw(RESET) RESET Low ts(Hi-ZRESET) High-Z
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Power on Reset Characteristics All card status are reset automatically when V CC voltage goes over about 2.3 V.
Parameter -CE setup time VCC rising up time Symbol tsu(VCC) tpr Min 100 0.1 Typ -- -- Max -- 100 Unit ms ms Test conditions
Power on Reset Timing
tpr Vcc tsu(vcc)
-CE1, -CE2
Attention for Card Use
* In the reset or power off, all register informations are cleared. * All card status are cleared automatically when V CC voltage turns below about 2.5V. * Notice that the card insertion/removal should not be executed during host is active, if the card is used in True IDE mode. * After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot access during +RDY/-BSY pin is "low" level. Flash card can't be operated in this case. * Card removal or power off should not be done during internal operations. When the removal or power off occurred during internal operation, there is the possibility that data are lost. * Before the card insertion VCC can not be supplied to the card. After confirmation that -CD1, -CD2 pins are inserted, supply VCC to the card. * -OE must be kept at the VCC level during power on reset in memory card mode and I/O card mode. -OE must be kept constantly at the GND level in True IDE mode.
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Physical Outline
Unit: mm 26 pin 1.60 0.05 1 pin (Top) 1.27 1.27 25 pin 50 pin 1.00 0.05
1.00 0.08 3.30 0.10 12.00 0.10
1.00 0.08 3.30 0.10
42.80 0.10
25.78 0.08
36.40 0.15
2.40 0.08
(Top)
(Top)
(Top)
41.66 0.13
0.60 0.08
66
0.80 0.08
3.00 0.08
HB288256/192/160/128/096/064/032C5
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
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For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585160
Copyright (c) Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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